1. Field of the Invention
The present invention relates to the field of digital to analog converters (DACs).
2. Prior Art
One approach to dynamic element matching in a pipelined analog to digital converter (ADC) stage is illustrated in FIG. 1. In this Figure, the reference ladder provides 16 equally spaced reference voltage levels, typically using a corresponding resistor ladder. The comparator bank contains an equal number of comparators, and compares the input signal with each of the reference levels to provide an equal number of outputs. In FIG. 1, a four bit flash ADC is illustrated, so that the output of the comparator bank is a 16-bit code. The code is called a thermometer code because any such output will be characterized by all bits of the code corresponding to reference voltage levels below the input voltage will be of one state, and all bits thereafter corresponding to reference voltage levels above the input voltage will be of the opposite state.
A multiplying digital to analog converter (MDAC) of FIG. 1 may look like the circuit in FIG. 2. On clock phase 1 (ø1), the input is sampled onto the input capacitor array and the feedback capacitor CFB is reset by closure of the switch across the feedback capacitor. At the end of ø1, the sample switches are opened and the comparator bank is strobed to latch the thermometer code. During ø2, the 16 thermometer code signals from the ADC are randomized by the code randomizer (See FIG. 1) and after randomization, are each used to drive a respective MDAC switch to connect the capacitor array elements to ±VREF, depending on the state of the respective thermometer code signal. The goal of the randomizer is to reduce distortion caused by mismatch in the capacitor array by randomly or pseudo-randomly coupling each capacitor of the capacitor array to different comparator bank outputs, sample time to sample time.
The difficulty with this approach is that the time available for op-amp (FIG. 2) settling is reduced by the delay through the randomizer. One possible randomizer consists of several stages of “butterfly” swappers. For a 16 threshold flash ADC, 4 stages are desired. This results in 4 series switches between the comparator bank and the capacitor array. Thus, traditional approaches to dynamic matching reduce the time allowed for amplifier settling, which requires faster amplifiers and ultimately limits sample rate.